1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and, more particularly, to a method of forming a gate in a non-volatile memory device.
2. Description of the Related Art
Semiconductor memory devices are generally divided into a random access memory (RAM) such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) which is referred to as volatile memory because the data stored on the cell is destroyed if the power is interrupted and a read only memory (ROM) which is referred to as non-volatile memory because the stored data on the cell is retained even when the power is temporarily interrupted.
Because the non-volatile memory device can store data for an unlimited time, there is an increased demand on a flash memory device such as electrically erasable and programmable ROM (EEPROM) capable of inputting and outputting data electrically. Memory cells of these devices generally have a vertical stack gate structure comprising a floating gate formed on a silicon substrate with a tunnel oxide layer disposed therebetween. Further, the stack gate structure includes a control gate over and/or around the floating gate with an intergate dielectric layer disposed therebetween. In the flash memory cell having this structure, a programming operation is accomplished by forming channel hot electrons on the drain side to accumulate the electrons in the floating gate, thereby increasing a threshold voltage (Vth) of a cell transistor. An erasing operation is performed by generating a high voltage between the substrate and the floating gate to discharge the electrons accumulated in the floating gate, thereby lowering the threshold voltage (Vth) of the cell transistor.
The floating gate affects the charge characteristics of the tunnel oxide layer during the programming and/or erasing of data and is typically formed of a doped polysilicon layer.
The intergate dielectric layer maintains charges stored in the floating gate and typically comprises an ONO layer formed by stacking a lower oxide film, a nitride film and an upper oxide film.
The control gate is a layer to which a voltage is applied to transfer electrons of the substrate to the floating gate or electrons in the floating gate to the substrate during the programming or erasing operation. The control gate is typically formed of a polycide structure having a polysilicon layer and a metal silicide layer stacked on the polysilicon layer to reduce resistance.
Generally, a polysilicon film used for the control gate is deposited at a crystalline phase at a temperature of about 620° C. and subsequently doped with a high concentration N-type impurity by POCl3 diffusion or ion implantation. However, where the POCl3 diffusion progresses with a high concentration (1E21/cm3), the morphology of the polysilicon film becomes poor because the polysilicon film is subject to the doping process for a long time at a high temperature of about 850° C.
On the contrary, where the POCl3 diffusion progresses with a low concentration (1E19˜1E20/cm3), a depletion layer in the polysilicon film increases, lowering the program speed. Furthermore, the grains in the polysilicon film have various sizes such that a bird's beak extends to a central portion of the ONO layer during a subsequent gate oxidation process for curing damage to the sidewalls of the ONO layer. Thus, as shown in the following table 1, the thickness variation of the ONO layer severely deteriorates the endurance and bake-retention characteristics of the non-volatile memory device. The endurance (i.e., the number of times in which program and erase operations can be repeated) represents a Vth variation of the cell transistor with respect to program-erase cycle and the bake-retention represents a Vth variation of the cell transistor measured after baking at a temperature of about 250° C.
TABLE 1Thickness, leftThickness,Thickness, rightThicknesssidecentersidevariationUpper oxide78 Å48 Å64 Å30 ÅNitride flim41 Å48 Å46 Å 7 ÅLower oxide55 Å53 Å70 Å17 Å
As shown in the table 1, the bird's beak phenomenon is most severe at the interface between the ONO layer and the control gate polysilicon layer. The control_gate polysilicon layer is typically formed by depositing undoped polysilicon and the subsequent POCl3 doping. This prior art method increases the thickness variation of the upper oxide film in contact with the control gate polysilicon layer.
To address this problem, the control gate is formed of in-situ doped polysilicon capable of easily controlling the doping level. Examples of this method are disclosed in Korean Patent Laid-Open Publication No. 2001-8614, Korean Patent Laid-Open Publication No. 2001-4262, and Japanese Patent Laid-Open Publication No. 2001-53171. Particularly, Korean Patent Laid-Open Publication No. 2001-8614 discloses a method of performing an annealing process after patterning the stacked gate structure including the control gate comprising an in-situ doped polysilicon.
If the in-situ doped polysilicon control gate is employed, the depletion layer in the polysilicon film is suppressed to a thickness of about 6 Å, thereby increasing the program speed. However, although this initially deposited in-situ doped polysilicon film is amorphous, the amorphous polysilicon film becomes crystallized (phase transformation) during a gate oxidation process performed after the gate patterning process. Accordingly, the thickness variation of the ONO layer caused by the bird's beak phenomenon is severe with the above described prior art method, thus deteriorating the reliability of the ONO layer and in turn degrading the endurance and the bake-retention characteristics of the non-volatile memory device.
FIG. 1A shows the bake retention characteristic according to a first conventional method where POCl3 doping is performed after depositing the undoped polysilicon. FIG. 1B shows the bake-retention characteristic according to the second conventional method of forming the control gate including using the in-situ doped polysilicon.
In the graphs, a graph shown by a symbol ♦ shows the variation of the program threshold voltage Vth with respect to the program-erase operation after 1 cycle. A graph shown by a symbol ▪ shows the variation of the program threshold voltage Vth with respect to the program-erase operation after 10000 cycles. A graph shown by a symbol ▴ shows the variation of the program threshold voltage Vth after the baking process. The horizontal axis indicates a program threshold voltage Vth and the vertical axis indicates the number of failed bits.
Referring to FIGS. 1A and 1B, in the second conventional method, the thickness variation of the ONO layer caused by the gate oxidation process is severe because the silicon bonds of amorphous phase are more unstable than the silicon bonds of crystalline phase and, thus, easily oxidized. Therefore, as compared with the first conventional method, the program threshold voltage Vth distribution and the range of fluctuation in the program threshold voltage Vth after baking increase in the second conventional method.
With the control gate comprising in-situ doped polysilicon, a depletion layer in a polysilicon film can be suppressed and the program speed can be increased. However, the reliability of the ONO layer deteriorates, thus degrading the endurance and bake retention characteristics.
Accordingly, a need still remains for a method for fabricating a gate structure in a non-volatile memory device without having the problems described above.